🏠 Atari Jaguar Developer Reference ▸ CPU (68000) ▸ Motorola 68000 — Programmer’s Model

Motorola 68000 — Programmer’s Model

The general-purpose CPU at the center of the Jaguar. This page covers the programmer-visible model only — registers, data organization, addressing modes, the instruction set, instruction timing, and exception processing — with Jaguar-specific details noted inline.

Source: Motorola MC68000 Family Programmer’s Reference Manual (M68000PRM) and MC68000 User’s Manual — the canonical, public 68000 architecture. This is not part of the Atari Jaguar documentation set; it is included so the console is documented end-to-end. Cycle counts are clock-cycle figures from Motorola’s timing tables (independent of clock frequency). For exhaustive per-instruction, per-addressing-mode timing matrices, consult §8 of the MC68000 User’s Manual.

On this page: The 68000 in the Jaguar · Registers · Status register · Data organization · Addressing modes · Instruction set · Condition codes (cc) · Instruction timing · Exception processing

The 68000 in the Jaguar

• Clock: ≈ 13.3 MHz (NTSC), derived from the system clock by the boot code’s clock dividers — do not touch CLK1/CLK2/CLK3 (see Memory Map → do-not-touch registers).
• Buses: 16-bit external data bus, 24-bit address bus → 16 MB address space. Internally the registers and most operations are 32-bit; a 32-bit memory access is performed as two 16-bit bus cycles.
• Byte order: big-endian (Motorola order) — the most-significant byte is at the lowest address. This matches the convention the Jaguar ASICs are set to (G_END/D_END = $00070007).
• Role: the 68000 is the system manager, not the performance path — heavy work belongs to the GPU/DSP/Blitter (see Architecture Overview). For maximum RISC throughput it can be halted to free the bus (see GPU → Performance notes).
• Jaguar memory rules: put the stack near the top of RAM (commonly $1FFFFC); cartridge programs start at $802000; in the dev environment the lower 16 KB (below $4000) is reserved (see Memory Map).
• Jaguar gotchas: the 68000 clr.l <ea> and move.l …,-(An) instructions corrupt writes to GPU/DSP register/RAM space — use the GPU/DSP or Blitter to write there instead (see Hardware Bugs & Warnings). Audio is muted after reset until bit 8 of JOYSTICK is set.

Registers

The processor has two privilege states: supervisor (full access, own stack SSP) and user (restricted; certain instructions are privileged). The Jaguar boot code runs in supervisor mode.

Status register

 15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
  T   0   S   0   0  I2  I1  I0   0   0   0   X   N   Z   V   C
 └──── system byte ────────────┘ └──────── CCR (user byte) ─────┘

The low byte alone is the CCR (condition-code register). The system byte (T, S, I) is only writable in supervisor mode.

Data organization

• Operand sizes: byte (8 bits), word (16 bits), long word (32 bits).
• Alignment: instructions and word/long operands must be at even addresses. A word or long access to an odd address raises an address-error exception. Bytes may be at any address.
• Memory layout (big-endian): for a long word at address A, byte A is the most-significant byte and A+3 the least; the word at A is the high word.

Addressing modes

SR, CCR, and USP are accessed by dedicated instructions rather than as general effective addresses. Xn (the index) may be a data or address register used as word (sign-extended) or long.

Instruction set

The instruction set groups below list each mnemonic, its operation, the operand sizes it supports, and how it affects the condition codes.

CCR effect key: * = set according to the result · — = unaffected · 0 = always cleared · 1 = always set · U = undefined. Columns are X N Z V C.

Data movement

Integer arithmetic

† ADDA/SUBA (address-register destination) do not affect the condition codes. ADDX/SUBX clear Z only if the result is non-zero (used for multi-precision).

Logical

Shift & rotate

Register-form shifts take a count of 1–8 (immediate) or a count in Dn (mod 64); memory forms shift by one bit and operate on a word only.

Bit manipulation

Z is set from the original value of the addressed bit. Bit number is mod 8 for a memory (byte) destination, mod 32 for a Dn (long) destination.

Binary-coded decimal

Program control

System control (mostly privileged)

The Jaguar’s GPU/DSP can be parked with the 68000’s STOP to free the bus — see GPU → Performance notes.

Condition codes (cc)

Used by Bcc, DBcc, and Scc (cc selects the test):

¹ T/F are not allowed on Bcc (use BRA for “always”); DBT/DBF (a.k.a. DBRA) and ST/SF are valid.

Instruction timing

Timing is given in clock cycles; at the Jaguar’s ≈13.3 MHz a cycle is ≈75 ns. The minimum bus (read or write) cycle is 4 clocks, so cycle counts are always multiples of 2 (and usually of 4). Motorola’s notation n(r/w) means n total clock cycles comprising r read and w write bus accesses.

Many instruction times are a base time plus the effective-address (EA) calculation time of the operand. Compute the EA time from the table below and add it where the standard table marks a +.

Effective-address calculation times

Representative instruction times

Register-to-register and the common cases (add the EA time where shown):

These are the standard figures; the complete per-instruction, per-mode matrices (including the full MOVE source×destination tables) are in §8 of the MC68000 User’s Manual.

Exception processing times

Exception processing

On an exception the 68000 switches to supervisor mode, pushes context onto the SSP, and vectors through a 256-entry vector table at the base of memory (each entry a 32-bit address; vectors 0–1 hold the reset SSP and PC).

Interrupts: seven priority levels; the I2–I0 mask in SR inhibits levels at or below its value. Level 7 is non-maskable. On the Jaguar, the video/timer interrupts reach the 68000 through the interrupt-control registers — see INT1/INT2 and VI in the Memory Map and the Object Processor refresh interrupt. On a development console the Alpine board’s Stop button generates a non-maskable interrupt.

Keep 68000 interrupt handlers (especially the vertical-blank handler) short — a long handler can starve the CD read path; see CD-ROM Programming Guide → the latency rule.

See also

• System Architecture Overview — the 68000 as system manager
• Memory Map / Register List — address space, INT1/INT2, clocks
• Hardware Bugs & Warnings — the clr.l/move.l GPU-space corruption
• Cartridges, EEPROM Saves & ROM Building — the $802000 entry point
• RISC Instruction Set (GPU/DSP) — the coprocessors’ very different ISA
• GPU → Performance notes — halting the 68000 to free the bus

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