🏠 Atari Jaguar Developer Reference ▸ Jerry — Sound & I/O ▸ Serial I/O — ComLynx, MIDI, Synchronous Serial

Serial I/O — ComLynx, MIDI, Synchronous Serial

Jerry provides an asynchronous UART (for ComLynx networking and MIDI), a synchronous serial interface, and the joystick / general-purpose IO decodes.

Source: Software Reference Manual — Tom & Jerry (V10), pp. 78–82. © Atari Corp. 1995.

Asynchronous Serial Interface (ComLynx and MIDI)

The asynchronous serial interface consists of two wires: UARTI (receive data input) and UARTO (transmit data output). It is primarily designed to support ComLynx but can also be used for MIDI transmit and receive. A prescaler register allows programmable baud rates.

Both transmitter and receiver are double-buffered: a character can be written to the data register before the previous character has finished transmitting, and a second character can be received before the previous one has been read.

Parity may be ODD, EVEN, or none. Parity on both input and output can be programmed active high or low (the printed format diagram shows active-low polarity; the diagram itself is (illegible) in the source).

Two classes of interrupt can be generated, each individually enabled:

• Receiver interrupts: Parity Error, Framing Error, Overrun Error, Receive Buffer Full.
• Transmitter interrupts: Transmit Buffer Empty.

Register naming caveat. The source documents these registers as ASICLK, ASICTRL, ASISTAT, and ASIDATA. The task references them as ASICLK1, ASICTRL1, ASISTAT1, ASIDATA1 (the numbered ComLynx-channel naming). These ASI registers were dropped from the latest JAGUAR.INC include file, so a current build environment may not define them — see the UART bug caveat below. Register descriptions are reproduced from the manual as printed.

ASICLK — Asynchronous Serial Interface Clock ($F10034, RW)

16-bit register determining the baud rate:

Clock Frequency = System Clock Frequency / (N + 1)

where N is the value written. The generated frequency is further divided by sixteen to give the baud rate.

ASICTRL — Asynchronous Serial Control ($F10032, WO)

All unused bits are reserved and should be written 0.

ASISTAT — Asynchronous Serial Status ($F10032, RO)

All unused bits are reserved and may return any value.

ASIDATA — Asynchronous Serial Data ($F10030, RW)

When read, returns the last character received in bits [0..7] and zero in bits [8..15]. The act of reading clears the receive-buffer-full condition, allowing subsequent characters to be received.

When written, bits [0..7] are transmitted from the UARTO pin. Bits [8..15] are unused and should be written as zeros.

UART Bug Caveat

There is a bug in the Jaguar UART. If a start bit is detected at a certain phase in the UART’s divide-by-16 timer, it will be shifted twice, resulting in a left shift of the data byte.

Workaround: Precede a data packet with a dummy byte whose MSB is set (e.g. $80); the receiver code should discard this dummy byte. Subsequent bytes should be aligned (i.e. exactly 2, 3, or 4 stop bits before the next start bit). This causes the falling edge of the next start bit to miss the phase of the UART counter that triggers the problem.

If a gap longer than 2 bit-times is left after a byte, or a byte is not exactly aligned with the previous one, the dummy byte must be re-transmitted to re-align the UART counter.

This bug is the reason the ASI registers were removed from the latest JAGUAR.INC.

Synchronous Serial Interface

The synchronous serial interface is controlled by seven registers, all within the DSP’s local address space, so the DSP may access them without external bus overhead. Other processors may access them at these addresses. All transfers should be 32-bit, though the registers themselves are only 16-bit. This interface carries the I²S audio stream (transmit/receive sample registers, serial clock, and word strobe).

The serial clock frequency is System Clock / (2 * (N+1)). SMODE bit 0 (INTERNAL) enables the clock and word strobe outputs; interrupts can be generated on the rising/falling edge of the word strobe or on the MSB of every word. Full register-level details, including the audio sample path, are documented in Audio Subsystem & Synthesis.

Joystick Interface

Jerry has four outputs which together control four external TTL ICs to provide the joystick interface. There are two registers.

JOYSTICK — Joystick Register ($F14000, RW)

When read, the joystick input buffers are enabled and the data reflects the state of the sixteen joystick inputs. Output JOYLO is asserted (active low) during the read.

When written, the low eight data bits are latched into the joystick output latch, and output JOYL2 is asserted (active low) during the write. The most significant bit (bit 15) enables the joystick outputs; this bit is cleared (disabled) by reset. Output JOYL3 is the inverse of the value in bit 15.

Bit 8 of this register is the audio mute control — see Audio Subsystem & Synthesis.

JOYBUTS — Button Register ($F14002, RW)

When read, the button input buffer is enabled and the data reflects the state of the four button inputs. Output JOYL1 is asserted (active low) during the read.

General Purpose IO Decodes

Jerry has six general-purpose IO decode outputs, asserted (active low) in the following address ranges. The term “General Purpose” is a misnomer because most of the outputs are reserved.

See also

• Audio Subsystem & Synthesis
• Digital Sound Processor (DSP)
• Controllers & Controller Ports
• Memory Map / Register List

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