🏠 Atari Jaguar Developer Reference ▸ Jerry — Sound & I/O ▸ Audio Subsystem & Synthesis

Audio Subsystem & Synthesis

Jerry produces stereo 16-bit audio by streaming DSP-generated samples to a synchronous (I²S) serial DAC interface, clocked by programmable timers and frequency dividers.

Source: Software Reference Manual — Tom & Jerry (V10), pp. 75–78; Technical Reference Manual (V10), p. 31; Appendix (Atari original, 26 April 1995), Appendix A. © Atari Corp. 1995.

Overview

The Jaguar console includes a stereo 16-bit audio subsystem. Digital audio data can only be sourced from the Jerry DSP. This data can also be monitored at the expansion or DSP ports, on the TXD serial data line. Jerry can also read serial digital audio data on its RXD pin.

The bit clock and word strobe signals can be sourced by Jerry, the expansion port, or the DSP port. If the clock source is not Jerry, software must force the Jerry clock lines tristate by clearing bit 0 (INTERNAL) of SMODE.

Among Jerry’s audio-related functions are:

A second RISC processor (the DSP) principally intended for sound synthesis.
Frequency dividers for clock synthesis.
Two programmable timers.
A stereo PWM DAC (requires few external components).
A synchronous serial interface and baud-rate generator (I²S).

Sound is produced by the DSP writing samples to the transmit DAC registers; the synchronous serial interface shifts them out at the rate set by SCLK and the word strobe. Timer 1 is conventionally used to generate the sample-rate interrupt that drives synthesis, and Timer 2 to generate a music-tempo interrupt.

Warning: the PWM DACs are not usable on the production console. Although Jerry contains a stereo PWM DAC, its outputs are not connected on the retail Jaguar — do not use them. Drive audio through the I²S synchronous serial interface instead. (Source: Appendix A — Frequently Asked Questions About Jaguar, “About hardware features.”)

Audio muted after reset. The audio mute function allows non-audio serial data to be transmitted by Jerry without making a horrible noise on the audio outputs. When serial peripherals are connected to the DSP port and in use, audio should be muted by writing zero to bit 8 of the JOYSTICK register ($F14000). Audio output is therefore enabled via bit 8 of JOYSTICK.

Frequency Dividers

Jerry synthesises three important clocks. Three write-only registers control the divider logic; the ratio between the video clock and the pixel clock is determined by Tom.

Chroma Clock — 4.43 MHz for PAL, 3.58 MHz for NTSC; should have a 50% duty cycle.
Video Clock — a multiple of the pixel clock (typically 6–12 MHz); must be tied to the chroma clock to avoid the “wood grain” effect on TVs.
Processor Clock — determines the speed of the memory interface, the Graphics Processor, the Object Processor, and the DSP. This clock is divided by two to provide a clock for an external processor.

These registers are marked “Do NOT Modify: For information only.”

Register	Description	Address	Access	Notes
`CLK1`	Processor clock divider	`$F10010`	WO	10-bit. Only used when the processor clock is generated by PLL. Frequency ratio between PCLKOSC and PCLKDIV; with PCLKDIV locked to CHRDIV, processor clock = (N+1) × CHRDIV. Initialized to 1 on reset. PCLKDIV pulses every N+1 PCLKOSC cycles.
`CLK2`	Video clock divider	`$F10012`	WO	10-bit. Only used when the processor clock is generated by PLL. Frequency ratio between VCLK and VCLKDIV; with VCLKDIV locked to CHRDIV, video clock = (N+1) × CHRDIV. Initialized to 0 on reset. VCLKDIV pulses every N+1 VCLK cycles.
`CLK3`	Chroma clock divider	`$F10014`	WO	6-bit. Divides the chroma oscillator (CHRIN/CHROUT) by N+1 to produce CHRDIV (50% duty cycle). Initialized to `$3F` (divide by 64) on reset. The MSB enables the chroma oscillator into the VCLK pin (clear on reset = output disabled).

For non-PLL synthesis the chroma crystal is some small multiple of the chroma carrier and this frequency is used as the video clock; CLK3 is written with the appropriate number and bit 15 is set to enable the crystal frequency into the VCLK pin.

Programmable Timers

Jerry contains two identical timers. Each consists of two 16-bit dividers:

The pre-scaler (first stage) divides the processor clock by N+1.
The divider (second stage) divides that frequency by M+1.

This gives frequency division in the range of roughly four to four billion. The outputs of the second stages may interrupt either the DSP or the external microprocessor (independently maskable).

It is intended that Timer 1 generates the sample-rate frequency for sound synthesis and Timer 2 generates the music-tempo frequency, though the timers may be used for other purposes. Writing the registers presets the counters (useful for programmable delays), and the registers are readable (useful for measuring time, profiling, or timing joystick events).

There are four registers; read addresses differ from write addresses. Pre-scalers and dividers are down counters, loaded when written and when they reach zero. When a divider reaches zero it may interrupt the DSP or CPU.

Register	Description	Address	Access
`JPIT1`	Timer 1 Pre-scaler	`$F10000`	WO
`JPIT2`	Timer 1 Divider	`$F10002`	WO
`JPIT3`	Timer 2 Pre-scaler	`$F10004`	WO
`JPIT4`	Timer 2 Divider	`$F10006`	WO

Jerry Interrupts

There are six interrupt sources which may interrupt the external microprocessor:

External — a rising edge on EINT[0] to Jerry may cause an interrupt.
DSP — the DSP may generate an interrupt by writing to a port.
Timers — both timers may generate interrupts.
Sync. — the synchronous serial interface can generate interrupts.
UART — the asynchronous serial interface can generate interrupts.

Typically only one or two sources are directed at the microprocessor; several are mainly of relevance to the DSP for sound synthesis. The interrupt control register enables, identifies, and acknowledges CPU interrupts from the six sources.

JINTCTRL — Interrupt Control Register (`$F10020`, RW)

Bit	Name	Description
0	`J_EXTENA`	Enable external interrupts.
1	`J_DSPENA`	Enable DSP interrupts.
2	`J_TIM1ENA`	Enable Timer 1 (sample rate) interrupts.
3	`J_TIM2ENA`	Enable Timer 2 (tempo) interrupts.
4	`J_ASYNENA`	Enable Asynchronous Serial Interface interrupts.
5	`J_SYNENA`	Enable Synchronous Serial Interface interrupts.
6	RESERVED	Set to 0.
7	RESERVED	Set to 0.
8	`J_EXTCLR`	Clear pending external interrupts.
9	`J_DSPCLR`	Clear pending DSP interrupts.
10	`J_TMR1CLR`	Clear pending Timer 1 (sample rate) interrupts.
11	`J_TMR2CLR`	Clear pending Timer 2 (tempo) interrupts.
12	`J_ASYNCLR`	Clear pending Asynchronous Serial Interface interrupts.
13	`J_SYNCLR`	Clear pending Synchronous Serial Interface interrupts.

Bits 0–5 enable the individual interrupt sources; when read, bits 0–5 indicate which interrupts are pending. Bits 8–13 clear pending interrupts from the corresponding source.

Synchronous Serial Interface (I²S Audio Output)

The synchronous serial interface is the path by which audio samples leave Jerry. It is controlled by seven registers, all within the local address space of the DSP, so the DSP may access them without external bus overhead. Other processors may access them at these addresses. All transfers should be 32-bit, though the registers themselves are only 16-bit.

SCLK — Serial Clock Frequency (`$F1A150`, WO)

8-bit register determining the frequency of the internally generated serial clock:

Serial Clock Frequency = System Clock Frequency / (2 * (N + 1))

where N is the value written.

SMODE — Serial Mode (`$F1A154`, WO)

Bit	Name	Description
0	`INTERNAL`	When set, enables the serial clock and word strobe outputs. (Clear this to tristate Jerry’s clock lines when an external clock source is used.)
1	RESERVED	Set to 0.
2	`WSEN`	Enables generation of word strobe pulses. When set, Jerry produces a word strobe output alternately high for 16 clock cycles and low for 16 clock cycles. When cleared, Jerry will not generate further high pulses. Ignored when `INTERNAL` is cleared.
3	`RISING`	Enables interrupt on the rising edge of word strobe.
4	`FALLING`	Enables interrupts on the falling edge of word strobe.
5	`EVERYWORD`	Enables interrupts on the MSB of every word transmitted or received.

Transmit / Receive Data Registers

Two 16-bit registers hold the data to be transmitted to the DACs. Note that the right/left registers are swapped on purpose for the *_DAC view:

Register	Description	Address	Access
`R_DAC`	Right transmit data (to DACs)	`$F1A148`	WO
`L_DAC`	Left transmit data (to DACs)	`$F1A14C`	WO

The same addresses are also presented in I²S-oriented form (the L/R order is not swapped here):

Register	Description	Address	Access
`LTXD`	Left transmit data (to I²S)	`$F1A148`	WO
`RTXD`	Right transmit data (to I²S)	`$F1A14C`	WO
`LRXD`	Left receive data (from I²S)	`$F1A148`	WO
`RRXD`	Right receive data (from I²S)	`$F1A14C`	WO

Note: the source lists the receive registers LRXD/RRXD with access “WO”; they hold received data and are read by the DSP. Reproduced as printed.

SSTAT — Serial Status (`$F1A150`, RO)

Bit	Name	Description
0	`WS`	Reflects the state of the word strobe pin. Do not use this to check for data ready — use the interrupt control register instead.
1	Left	(illegible)

Audio Subsystem & Synthesis

Overview

Frequency Dividers

Programmable Timers

Jerry Interrupts

JINTCTRL — Interrupt Control Register ($F10020, RW)

Synchronous Serial Interface (I²S Audio Output)

SCLK — Serial Clock Frequency ($F1A150, WO)

SMODE — Serial Mode ($F1A154, WO)

Transmit / Receive Data Registers

SSTAT — Serial Status ($F1A150, RO)

See also

JINTCTRL — Interrupt Control Register (`$F10020`, RW)

SCLK — Serial Clock Frequency (`$F1A150`, WO)

SMODE — Serial Mode (`$F1A154`, WO)

SSTAT — Serial Status (`$F1A150`, RO)